GIS

Xe plasma FIB (i-FIB) Delayering technology
using water as Gas-Assisting Etching (GAE) enhancer

Fast milling rates and high quality artifact-free surfaces are two essential and desired elements when preparing cross-sections in samples for the purposes of failure analysis. Gas introduction using a 5-line GIS coupled with i-FIB Orsay physics’ plasma ion source column reduces dramatically the time for cross-sectioning and planar etching from tens of hours or even days to a matter of hours.

The burgeoning generation of electronic data and the growing need for fast processing is driving the development of unique architectures in microelectronic devices. High device performance, along with low energy consumption, decreasing device area and optimal production costs are the four basic tenets of operation in the microelectronics industry [1]. These rules have led to ever-increasing area density of the basic elements in electronic devices and consequently to element’s shrinkage to the nanometer scale. This has brought new challenges for production technologies as well as for failure analysis of such devices.

State-of-the-art standard electronic devices are based on 22 nm and 14 nm node technology and the next generation of 10 nm and 7 nm nodes are already under development [1]. These technologies call for unique instruments and workflows for the identification and excavation of nanometer-sized faults buried under the device surface. Mechanical polishing as a standard tool in the failure analysis process does not meet the very strict requirements of these state-of-the-art nodes. The thickness of metal interconnects and dielectric separating layers just above the transistors has shrunk to less than 100 nm. Therefore it is a challenge to stop the polishing process in a particular layer with the expected quality, accuracy and repeatability. Moreover, mechanical polishing, mostly accompanied by surface artefacts like material chipping-off and site-specific fault excavation, is usually impossible. Focused Ion Beam (FIB) technology using has proven to overcome these restrictions. It offers the possibility to target a failure with nanometer accuracy in depth as well as in the lateral direction. Therefore cross-sectioning, site-specific layer-by-layer excavation (also known as delayering) and direct extraction of a Transmission Electron Microscopy (TEM) lamella containing the particular fault of interest have become standard methods in failure analysis.

This note presents delayering of a processor based on 14 nm node technology [2]. The delayering is performed with a Xe plasma focused ion beam (i-FIB column). Beam currents of Xe i-FIB up to 2 µA have extended the dimensions of the analyzed volume of interest to several hundred micrometers in general [3,4], while simultaneously enabling homogeneous delayering with nanometer accuracy. Xe source is advantageous also because interaction of inert Xe atoms with the material surface does not significantly alter either the properties or the reactivity of the material. Thus the ability of Xe to induce surface contamination is negligible.

Processor architecture is based on alternating metal and dielectric layers (Fig. 1). These layers have different sputtering rates when FIB delayering is applied. Uneven sputtering can be substantially controlled by chemical means. In our experiments, water vapor was delivered directly to the point of patterning via a 5-line GIS (Gas Injection System developed by Orsay Physics) in order to equalize sputtering of metal interconnects and insulators. The result of processor delayering down to the first metal layer, just above the transistors is shown in Fig. 2. The damage-free surface of the transistor contact layer is ready for electrical probing.

Nanometer-sized elements in state-of-the-art electronics have posed a challenge also for imaging technologies. Clear observation of the very thin individual layers means suppressing the acceleration voltage of primary electrons to the sub-1 kV range, ideally to 500 V. At higher energies, the electron signals from different layers would intermix as they are generated in a volume comparable to the thickness of those layers. However, sub-nm resolution at low electron energies is a necessary condition due to the size of the observed features. High resolution pictures captured at 500 V are shown in Fig. 2. Low-kV imaging has verified highly homogeneous delayering of the processor as can be seen by the absence of large contrast changes in the delayered region.

 

References

[1] http://www.itrs2.net/
[2] http://www.intel.com/content/www/us/en/silicon-innovations/intel-14nm-technology.html
[3] T Hrnčíř et al., 38th ISTFA Conf. Proc. (2012), p. 26.
[4] A Delobbe et al., Microsc. and Microanal. 20 (2014), 298.
[5] T Hrnčíř et al., 41th ISTFA Conf. Proc. (2015), p. 60.

 

 

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Figure 1. Processor (14 nm node) after mechanical
polishing and Xe i-FIB cross-sectioning.

 

Figure 2. Top view of the transistor contact layer in a commercial
Processor (14 nm node) after the delayering process obtained with
a TESCAN XEIA3 FIB-SEM system (i-FIB column).
A global overview (left) and close-up micrographs (right) are taken
with a SE detector at 500 V using beam deceleration mode.

Curtaining-Free Top-Down TEM Lamella Preparation
from a Cutting Edge Integrated Circuit using a
Rocking-Stage and water as Gas-Assisting Etching
(GAE) enhancer

Diminution of FIB polishing artifacts such as curtaining or delayered surface roughness is the key for the comprehension of the failures at the nanoscale dimension. The association of a specially designed Rocking stage, FIB columns and a 5-line GIS gives the possibility to reach smooth surfaces or curtaining-free cross sections suitable for advanced analysis such as TEM lamella preparation or semiconductor failure analysis.

Semiconductor industry continues to shrink sizes of the electronic devices. Currently commercial state-of-the-art technology node for integrated circuits is 14 nm, while 10 and 7 nm technology nodes are in the development stage [1]. Those integrated circuits are based on multigate transistors, where source-drain channel surrounded by a 3D gate. Failure analysis process of such integrated circuits typically involves inspection of TEM lamellae prepared by FIB-SEM machines from a single transistor layer.

One difficulty in preparation of such TEM lamellae is different ion milling rates of materials of the integrated circuits. In case of conventional top-down FIB polishing, this causes unwanted curtaining artefacts resulted mainly from the metal contacts above the transistor layer. One way to eliminate curtaining (see figure 1) is so called backside (or inverted) polishing technique which involves lamella extraction, flipping and polishing by FIB through the silicon layer [2]. However, this technique is too much time consuming for a daily semiconductor industry process.

A new technique of curtaining-free lamella preparation was found in the TESCAN ORSAY group. This technique allows for normal top-down FIB polishing through upper metal contacts while curtaining artefacts are eliminated by changing the incident angle of ion milling by rocking of the sample on a special TESCAN rocking stage.

In order to demonstrate this technique, we took the latest commercially available processor based on 14 nm technology node (Intel Pentium G4400) [3]. The processor wafer was decapsulated and mechanically polished to remove the top metal contacts. Further delayering (homogeneous layer etching) was performed by means of a specially developed technique of water-assisted plasma FIB etching (i-FIB column). The later technique allows uniform damage-free delayering down to the first metal layer which is just above the transistor layer (Fig. 2a). The delayered sample was transferred to a TESCAN GAIA3 FIB-SEM instrument which was equipped with a Ga FIB column (Cobra), a SEM column with immersion optics and a Rocking stage [4].

Initial steps of a lamella preparation involved a standard routine of platinum protection layer deposition using a 5-lines GIS developed by Orsay Physics, FIB trench milling, undercut and lamella transfer by a nanomanipulator to a TEM half-grid for the final thinning.

Lamella thinning was performed by Ga Cobra FIB at 30 kV till reaching the lamella thickness of 150 nm. The last step of thinning down to the thickness of less than 20 nm was performed by 5 and 2 kV FIB polishing (see perpendicular “fin-cut” for illustration on Fig. 2b). The final lamella was prepared just in the middle of a single fin (so called “gate-cut”). Moreover during the last steps of FIB thinning the lamella was milled from two directions on the Rocking stage (Fig. 3a). Thus due to continuous change of Ga beam incident angle (±15º) curtaining artefacts were eliminated.

Finally, the prepared lamella was transferred to a TEM microscope for observation. The observation demonstrated that even though the lamella was polished by Ga FIB by top-down technique through upper metal contacts it does not show evidence of any significant curtaining artefacts (Fig. 3b). This result proved the potential of the technique of top-down lamella thinning on a TESCAN Rocking stage.

 

References:

[1] http://www.itrs2.net/
[2] O Ugurlu, M Strauss, G Dutrow, J Blackwood, B Routh, C Senowitz, P Plachinda, and R Alvis, Proc. of SPIE 8681 (2013), p. 868107.
[3] http://www.intel.com/content/www/us/en/silicon-innovations/intel-14nm-technology.html
[4] T Hrnčíř, J Dluhoš, L Hladík, E Moyal, J Teshima, and J Kopeček, 40th ISTFA Conf. Proc. (2014), p. 136.

 

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Figure 1. Curtaining effect observed on a cross section

 

Figure 2. (a) Top view image of the first metal layer after delayering
by water-assisted Xe Plasma FIB (i-FIB on XEIA3) etching. (b) “Fin-cut”
of the chip illustrating the place and procedure of further lamella thinning.

 

Figure 3. (a)Thinning the lamella on a Rocking stage: altering
the ion incident angle by ±15º eliminates curtaining. (b) TEM image
of the lamella prepared in the middle of a single fin (“gate-cut”)
shows no significant evidence of curtaining artefacts.